A typical GPS receiver consists of an RF front end and a digital signal processor (DSP). The RF front end receives the GPS signal from the satellites, mixes it down to an intermediate frequency, and samples it.
The DSP acquires a lock to multiple GPS satellite signals present in the front end samples and tracks variations in the signals over time. While the DSP tracks variations in the signal, it also extracts information from it that can be used to compute the current position and time—the “navigation solution.”
Our lives are increasingly being affected by the use of GPS technology. We rely on GPS to navigate from one place to another, to locate a person or an object, to provide time synchronization in our telecommunication networks and power grids, and in many other every day applications. Today, high power consumption of existing GPS receiver chips can cause overheating issues, and can limit continuous GPS operation in mobile devices. It is clear that the high power consumption in GPS receivers must be addressed to pave the way for advances in areas such as location-aware applications and micro robotics navigation.
Significant research effort has been devoted to reducing the power consumption of the RF front end, with current designs having power consumption of less than 10 mW. However, more work needs to be done to lower the power consumption of the GPS baseband processor.
A powerful DSP can perform all baseband processing in software. This approach is highly reconfigurable and easy to develop and debug but not suitable for low power applications. An alternative is to use a hardware correlation engine to handle the fast correlation operations and a microprocessor to handle the rest of the signal processing tasks. For these approaches, more work also needs to be done to lower the power consumption of the GPS baseband processor.
There is a need for GPS chip designs with low power consumption.